A. Field of the Invention
The present invention relates to a semiconductor device such as a high voltage integrated circuit (HVIC) having a high voltage isolation structure that is a double-RESURF structure, and to a method of manufacturing the semiconductor device.
B. Description of the Related Art
In an industrial inverter, heretofore, a transformer or a photocoupler has been used for electrical insulation in order to gate drive a semiconductor device such as an IGBT configuring a power conversion bridge circuit. In recent years, in order to reduce cost a high voltage IC with no electrical insulation has been used mainly for low-power applications.
FIG. 16 is a common gate drive circuit diagram of a high voltage IC. High voltage IC (HVIC) 806 includes high side drive circuit 803 that operates using a power source Vb with an emitter potential (Vs) at the low potential side main terminal of upper arm IGBT 801 as a reference. Also, high voltage IC 806 includes level shifters 804 that transmit a signal to high side drive circuit 803 from a control circuit (not shown). Furthermore, high voltage IC 806 includes low side drive circuit 805 that drives lower arm IGBT 802 on receiving the signal from the control circuit, and operates using a power source Vcc with an emitter potential (COM) at the low potential side main terminal of lower arm IGBT 802 as a reference. Level shift resistances 807 are connected to level shifters 804, thus creating a mechanism wherein the signal from the control circuit is transmitted to high side drive circuit 803 by a current caused to flow through the level shift resistances 807 being controlled by level shifters 804. In order to reduce a power loss in level shifters 804, it is common to include two level shifters 804 for SET (ON) and RESET (OFF).
High voltage MOSFETs are normally used as level shifters 804. As the high voltage IC has to withstand an overvoltage generated as a result of a turning on/off of IGBTs or the like, a breakdown voltage of 600V or higher is required in the case of an AC 200V inverter, and a breakdown voltage of 1200V or higher is required in the case of an AC 400V inverter. In order to realize this high breakdown voltage, a RESURF structure is widely used in high voltage MOSFETs used as level shifters 804, and a double-RESURF structure suitable for a high breakdown voltage is often used in the case of an AC 400V inverter.
FIG. 17 is a model diagram of a double-RESURF structure. The double-RESURF structure has a configuration wherein n-type semiconductor region 102 is sandwiched by two p-type semiconductor regions 101 and 103.
A high breakdown voltage can be realized by regulating the net amount of impurities per unit area in a diffusion layer so as to satisfy the following expressions that are double-RESURF conditions, as described in “Design and Optimization of Double-RESURF High-Voltage Lateral Devices for a Manufacturable Process,” IEEE Trans. On Electron Devices, USA, IEEE, July 2003, vol. 50, no. 7, pp. 1697-1701.Qp≦1·4×1012[/cm2]Qn≦2·8×1012[/cm2]Qn−Qp≦1·4×1012[/cm2]  Expression 1Herein, Qn is the total amount of impurities per unit area in semiconductor region 102, and Qp is the net amount of impurities per unit area in semiconductor region 103.
The double-RESURF structure is suitable for a realization of a high breakdown voltage, but has a problem in that as its junction area is large, a parasitic capacitance is high. In FIG. 16, when the parasitic capacitance of MOSFETs configuring level shifters 804 is high, a sudden change in voltage generated as a result of a turning on/off of IGBTs 801 and 802, that is, so-called dV/dt noise, allows a large displacement current to flow through level shift resistances 807 via level shifters 804. Because of this, malfunction is liable to occur.
JP-A-2000-252809 describes a circuit of FIG. 18 as a circuit for solving the problem of malfunction due to the dV/dt noise. When the circuit is in normal operation, it does not happen that a voltage drop occurs simultaneously in two level shift resistances 807, but when the dV/dt noise comes into a line Vb, a voltage drop occurs simultaneously in the two level shift resistances 807 when the parasitic capacitances of two level shifters 804 are the same and the values of level shift resistances 807 are the same. The circuit of FIG. 18 is a circuit utilizing this, and is configured to prevent malfunction due to a displacement current by not carrying out a SET/RESET operation when a voltage drop occurs simultaneously in two level shift resistances 807.
FIGS. 19 to 20B are configuration diagrams of a heretofore known semiconductor device having a high voltage isolation structure that is a double-RESURF structure, wherein FIG. 19 is a main portion plan view, FIG. 20A is a main portion sectional view taken along line A-A of FIG. 19, and FIG. 20B is a main portion sectional view taken along line B-B of FIG. 19.
Semiconductor device 500 includes n-type diffusion layer 52 formed on a surface layer of p-type semiconductor substrate 51 and p-type diffusion layer 53 formed on a surface layer of n-type diffusion layer 52. Semiconductor device 500 includes p-type well region 54 formed on the surface layer of n-type diffusion layer 52 so as to be in partial contact with p-type diffusion layer 53 and gate electrode 65 disposed on p-type well region 54 via gate dielectric film 64. Semiconductor device 500 includes n-type source region 57 formed on a surface layer of well region 54 and n-type drain region 59 formed opposite p-type well region 54 in the vicinity of an end portion of p-type diffusion layer 53 on a surface layer of the n-type diffusion layer. N-type drain region 59 is connected to a high potential region by an bonding wire or the like (not shown). P-type diffusion layer 53 is formed having a uniform concentration in a lateral direction of semiconductor substrate 51. Reference numeral 59 in FIGS. 19 to 20B is a drain electrode, 60 is a source electrode, and 61a and 61b are field plates.
In the double-RESURF structure of the heretofore known semiconductor device 500 in FIGS. 19 to 20B, a junction capacitance Cp (parasitic capacitance) between n-type diffusion layer 52 and p-type diffusion layer 53 occupies a large portion of a junction capacitance Cds (parasitic capacitance) between n-type drain region 56 and n-type source region 57. As a configuration is such that the junction capacitance Cp is connected to n-type source region 57 via a diffusion resistance Rp of p-type diffusion layer 53, as shown in FIG. 20B, a displacement current Idis generated when the dV/dt noise is applied to the drain increases when Rp is low.
JP-A-2000-252809 describes that when a simultaneous voltage drop of the load resistances occurs in a level shift circuit that on/off drives an upper arm IGBT of an PWM inverter bridge circuit, malfunction due to dV/dt noise is prevented by providing a NOT circuit that masks an output pulse.
JP-A-2009-277776 provides a (miniaturized) MOSFET wherein a drift region and a RESURF region are formed in a wave shape in a source-drain direction, and a source-drain length is made shorter than heretofore known with a high breakdown voltage maintained.
JP-A-6-204482 describes a MOSFET wherein a RESURF region is formed in a wave shape in order to suppress an increase in ON resistance.
JP-A-2005-175063 describes that a p-type top region and n-type drift layer extend in parallel adjacent to each other, and positive holes flow into the top region and electrons flow into the drift layer, thereby maintaining the charge balance of the drift region in an ON state of the semiconductor device, thus improving a breakdown voltage.
However, as the values of two level shift resistances 807 are normally not completely equal due to process variations in the circuit of FIG. 18, it is not possible to sufficiently prevent malfunction due to the dV/dt noise.
Also, even when level shift resistances 807 are the same, a displacement current flowing through the parasitic capacitance of MOSFET 804 configuring the circuit (the level shifters and the like) increases when dV/dt is great. The displacement current flows through level shift resistances 807, thus increasing a voltage drop in level shift resistances 807. By so doing, a buffer circuit of FIG. 18 is logically inverted, and malfunction of the circuit due to the dV/dt noise occurs.
Also, in the circuit of FIG. 16 too, in the same way, when a displacement current flowing through the parasitic capacitance of MOSFET 804 increases, an RS-FF circuit is logically inverted, and malfunction of the circuit due to the dV/dt noise occurs.
JP-A-2000-252809, JP-A-2009-277776, JP-A-6-204482, and JP-A-2005-175063 do not describe a semiconductor device such that it is possible to reduce a displacement current due to dV/dt by forming a shallow p-type diffusion layer on a double-RESURF structure surface of high concentration regions and low concentration regions, and increasing the lateral resistance of the p-type diffusion layer without changing the amount of electric charges achieving a charge balance.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.